Standard semiconductor devices may be less suitable, e.g. may be unsuitable, for use in harsh media conditions, e.g. under exposure to sulfuric or fuming nitric acids or to iodine. For example, bond pad metals, such as aluminium or copper, may corrode, e.g. due to oxidation, when exposed to such chemicals. It is known in the art to cover the bond pads by a protective gold layer. However, a diffusion barrier may be needed in between the bond pad and the gold. For example, without a diffusion barrier, aluminium and gold may easily and rapidly diffuse into each other, which may be even more problematic in high temperature applications. Providing a protective noble metal layer of gold, palladium or platinum on the device allows to maintain the advantages of standard CMOS processing in a device for harsh media conditions, such as an efficient volume production and a good electrical contact between the interconnect metal and an integrated circuit in the silicon. However, ensuring the integrity of the adhesion layer and the diffusion barrier when the device is exposed to the harsh environment remains challenging.
FIG. 1 shows a cross section of an exemplary integrated circuit semiconductor device, e.g. a hybrid pressure sensor, for harsh media as known in the art. In such hybrid pressure sensor, a bond wire 136 can be used to electrically connect a sensor 130 to a CMOS interface chip 120. Another exemplary bond wire 126 may connect the CMOS interface chip to a substrate 110, such as a leadframe or printed circuit board (PCB). The wires 126,136 may be protected for harsh media by a mould compound 140. During the moulding, a cavity on top of the device can be created, in which the sensor 130, e.g. a pressure sensor, can be mounted. Thus, the bond wire 136 can be provided in this cavity to connect a sensor bond pad 132 to a bond pad 122 of the CMOS interface chip.
For example, it is known in the art to provide the bond pad 122 of the CMOS interface chip in the cavity, and covering the aluminium of this bond pad 122 by a gold layer 124. Likewise, the bond pad 132 of the sensor 130 may be covered by a gold layer 134. Alternatively, as shown in FIG. 2, it is also known in the art to cover the bond pad 222 of the CMOS interface chip by the mould compound 140. In such prior-art devices, the gold layer 224 covering the CMOS bond pad 222 may extend into the cavity, thus acting as a signal conductor between the bond pad 222 and the bond wire 136 that is resilient to the harsh environment. This type of extension is known in the art as a ‘redistribution’ of the bond pad. This has the advantage that the mould compound protects the interface from bond pad to redistribution.
It is known in the art to deposit gold onto an aluminium bond pad by electroless plating, e.g. first a layer of nickel is grown on the aluminium bond pad, followed by electroless plating of a thin gold layer. The nickel may then form a suitable diffusion barrier. However, while the layers provided on the bond pad by an electroless plating method may firmly adhere to the bond pad metal, no mechanical connection is realized between the protective layers and the passivation around the bond pad. This has the disadvantage that chemicals, such as the aforementioned chemicals that can be present in harsh media, may penetrate the interface between the passivation and the plated metals and corrode the bond pad metal. For example, a mechanical and chemically resistant connection between the gold layer and the passivation could be highly advantageous.
For example, EP 1947439 describes a deposition of gold on a TiW barrier of a bond pad by electroless plating. The method described in EP 1947439 may have the disadvantage that harsh media such as iodine may still penetrate between the passivation layer and the gold and attack the TiW layer. Once the TiW is etched, the aluminium will be exposed to the iodine and can be etched very quickly. Furthermore, since the silicon substrate is not completely covered with passivation, galvanic corrosion can also take place through the interface, e.g. by an electron exchange partly through the substrate.
It is furthermore known in the art to deposit gold by electroplating. For example, a seed layer may be deposited over the entire substrate to distribute the plating current over the substrate. This seed layer remains between the CMOS metal and the layer that is plated on top of the seed layer. The seed layer normally serves as an adhesion layer, a diffusion barrier between the CMOS metal and the metal plated on top, and as a low resistive layer for a uniform current distribution during plating. Therefore, often TiW, Ti or TiN is sputtered first to provide an adhesion and barrier layer, followed by the sputtering of a highly conductive layer such as gold or copper to allow high plating currents. The sputtered seed layer can advantageously also form a solid mechanical connection to a silicon nitride passivation. This strong adhesion may result from the kinetic energy of the sputtered metal atoms hitting the substrate. Unfortunately, organic mould materials may not adhere well to the seed layer when a noble metal is used. It is furthermore known in the art to sputter a second adhesion layer on top of a highly conductive noble metal layer to ensure a good adhesion of the plating to a mould.
However, after the electroplating of the gold on the bond pads, the seed layer needs to be etched away to ensure that no electrical connection between different structures remains, such that the edge of the seed layer at the bottom of the gold structure is exposed to the environment, e.g. to the aforementioned corrosive chemicals in a harsh media application. It is known to apply an additional organic protection layer after etching the seed layer to cover the exposed edge of the seed layer. However, such protection layers may have a poor adhesion to gold, and corrosive chemicals may yet penetrate the interface between the protection layer and the gold metal.
Another disadvantage of known strategies in which the bond pads are covered with gold is that standard CMOS passivation is relied upon to protect the interconnect, e.g. the aluminium or copper interconnect. This passivation may however be insufficient to block the aforementioned corrosive chemicals. For example, particularly iodine may tend to completely remove aluminium wires when only one small defect, e.g. a small pinhole, is present in the passivation layer covering the interconnect. For that reason, it is known to cover the passivation with an additional layer such as polyimide. Such an extra passivation layer may be referred to as a ‘repassivation layer.’ Such repassivation layer may be opened at the bond pads with an opening that is smaller than the passivation bond pad opening. The seed layer may then be sputtered on top of this polyimide layer.